1. Field of the Invention
This invention relates to a digital/analog converter circuit and a liquid crystal display (LCD) incorporating the digital/analog converter circuit and relates in particular to a so-called drive-circuit-integrated liquid crystal display in which a reference voltage selector type digital/analog converter circuit and a drive circuit containing this digital/analog converter circuit are integrally formed on a substrate on which polysilicon thin film transistors are arrayed in a matrix as switching devices for the pixels.
This invention also relates to a level shift circuit, a shift register using this level shift circuit and a liquid crystal display device incorporating this level shift circuit and shift register, and relates in particular to a level shift circuit having a basic structure comprised of CMOS latch cells, a shift register utilizing this level shift circuit in each level shift of the clock signal at each transfer stage, and a so-called drive-circuit-integrated liquid crystal display incorporating this level shift circuit or shift register as a circuit to configure the scanning circuit.
This invention also relates to a sampling latch circuit, a latch circuit and a liquid crystal display (LCD) incorporating the latch circuit and relates in particular to a sampling latch circuit having a level shift function and a basic structure comprised of CMOS latch cells, a latch circuit and a so-called drive circuit-integrated liquid crystal display device incorporating the sampling circuit and the latch circuit as circuits to configure the scanning circuit.
2. Description of the Related Art
A digital interface drive circuit integrated onto the same substrate as the pixel section by thin film transistors (TFT) and comprising a drive-circuit-integrated liquid crystal display of the related art is shown in FIG. 34. First and a second horizontal drives 702, 703 are mounted above and below an effective pixel region 701 arrayed with pixels in a matrix, and for instance, a vertical drive system 704 is installed on the left side in FIG. 34 and integrated onto the same substrate (hereafter called LCD panel) along with the effective pixel region 701 of thin film transistors.
The first horizontal drive 702 is comprised of a horizontal shift register 721, a sampling & first latch circuit 722, a second latch circuit 723 and a DA (digital/analog) converter circuit 724. The second horizontal drive 703 is comprised, the same as the first horizontal drive 702 of a horizontal shift register 731, sampling & first latch circuit 732, a second latch circuit 733 and a DA (digital/analog) converter circuit 734. The vertical drive system 704 is comprised of a vertical shift register 741.
A significant problem that occurs when the above described drive circuit/liquid crystal display device of the related art is fabricated is the size of the surface area forming the drive circuit on the LCD panel or in other words, the peripheral area (hereafter called the picture frame) of the effective pixel region 701. The circuit surface area of the DA converter circuits 724, 734 is particularly important because the size of the LCD panel picture frame is determined by these DA converter circuits 724, 734 area. A reference voltage selector type is widely utilized as the DA converter circuit for the drive-circuit-integrated liquid crystal display. The reason being that the reference voltage selector type has less variation in terms of output voltage potential.
The circuit structure of a reference voltage selector type DA converter circuit is shown in FIG. 35. This circuit shows a 3-bit 8-step DA converter structure. In this DA converter circuit as clearly shown in FIG. 35, step selector units 708-0 through 708-7 comprising a selector circuit 705, latch circuit 706 and decode circuit 707 are formed for each step (reference voltages Vref F0 through Vref7).
However, in the structure shown for the DA converter structure, since a latch circuit 706 and decoder circuit 707 are formed for each step, as clearly shown in the circuit structure of FIG. 35, an extremely large number of elements comprises the circuit so that when attempting to form a multi-step DA converter circuit of TFT components, the surface area of the circuit becomes extremely large. Consequently, when mounting the converter circuit on the liquid crystal display device, the LCD panel picture frame size is large, creating the problem that the overall device cannot be made compact.
A method was proposed for a circuit structure combining the reference voltage selector type DA converter circuit with a switching capacitor in order to reduce the size of the circuit surface area. However, this circuit structure required a buffer circuit so that the current consumption required just by the buffer circuit created the problem of a large increase in overall circuit power consumption.
An example of a level shift circuit comprised of CMOS devices is shown in the related art 1 in FIG. 13. In the level shift circuit of this related art 1, a CMOS latch cell 101A has a basic structure comprised of a an N channel MOS (hereafter simply NMOS) transistor Qn101A with a source connected to ground and a gate supplied by an input signal in1, an NMOS transistor Qn102A with a source connected to ground and a gate supplied with an input signal in2, a P channel MOS (hereafter simply PMOS) transistor Qp101A connected between power supply VDD and drain of NMOS transistor Qn101A with a gate connected to the drain of NMOS transistor Qn102A, a PMOS transistor Qp101A connected between the drain of NMOS transistor Qn102A and power supply VDD with a gate connected to the drain of the NMOS transistor Qn101A.
In the level shift circuit of the related art 1 for instance, a low voltage amplitude signal of 3 volts is input as signal in1, and a signal in2 is input as an inverted signal of in1. These low voltage amplitude three volt input signals in1 and in2 appear in the drains of the NMOS transistors Qn101A, Qn102A as the amplitude of the power supply VDD circuit. The respective drain outputs of the NMOS transistors Qn101A, Qn102A are output as an inverted output signal xout by way of the inverter 103A and an output signal out by way of the inverter 102A. In this way, the low voltage amplitude signals in1, in2 are level-shifted to a high voltage amplitude signal out and xout of the power supply VDD.
A level shift circuit of the related art 2 is shown in FIG. 14A. In the level shift circuit of this related art 2, a CMOS latch cell 201A has a differential amplifier structure comprised of a an N channel MOS (hereafter simply NMOS) transistor Qn201A with a source connected to ground and a gate supplied by an input signal in1, an NMOS transistor Qn202A with a source connected to ground and a gate supplied with an input signal in2, a diode-connected P channel MOS transistor Qp201A connected between power supply VDD and drain of NMOS transistor Qn201A, and a PMOS transistor Qp202A connected between the drain of NMOS transistor Qn202A and power supply VDD and sharing a common gate with the NMOS transistor Qp201A.
In the level shift circuit of the related art 2 for instance, a low voltage amplitude signal of 3 volts is input as signal in1, and a signal in2 is input as an inverted signal of in1. This low voltage amplitude three volt input signal in1 appears in the drains of the NMOS transistors Qn202A as the amplitude of the power supply VDD circuit. The drain output of the NMOS transistor Qn202A is output as an output signal out by way of the inverter 202A. In this way, the low voltage amplitude signal in1 is level-shifted to a high voltage amplitude signal out of the power supply VDD.
However, in the above level shift circuits of the related art 1 and 2, a voltage sufficient to tun on the NMOS transistors Qn101A, Qn201A or the NMOS transistors Qn102A, Qp202A is required as the amplitude of the input signals in1, in2. In other words, a transistor threshold voltage of Vth or higher is required and when this condition cannot be satisfied, the level circuit will not operate. Accordingly, when attempting to shift the level of the applicable circuit to the required high voltage by using a level shift circuit input comprised of an output signal for example of a CMOS-LSI device of approximately three volts utilizing a TFT (thin film transistor) with a large threshold voltage Vth, the problem occurs that a stable level shift sometimes cannot be obtained.
Also, though the level shift circuit of the related art 2 has a small area and high speed operation compared to the level shift circuit of the related art 1, since the PMOS transistors Qp201A, Qp202A comprise the current mirror circuit, when the NMOS transistor Qn202A is on, current is flowing in the PMOS transistors Qp201A, Qp202A so that the related art 2 has the problem of large current consumption.
The circuit structure shown in FIG. 15A was proposed to resolve the above problems with the level shift circuits with TFT (thin film transistors). This level shift circuit of the related art 3 was basically comprised of a CMOS latch cell 30 having a differential amplifier structure comprising NMOS transistors Qn301A, Qn302A, and PMOS transistors Qp301A, Qp302A. In this circuit, the input signals in1, in2 were not input as is, into the gates of the NMOS transistors Qn301A, Qn302A of the CMOS latch cell (differential amplifier) 301A, instead, an input was made to these gates after performing a DC shift to a level higher than the threshold voltage of these transistors.
In other words, the input signals in1, in2 were input to the NMOS transistors Qn301A, Qn302A by way of the NMOS transistors Qn303A, Qn304A. At the same time, signals with a polarity opposite the gate input of the NMOS transistors Qn301A, Qn302A, or in other words the input signals in2, in1 were input to the sources of the NMOS transistors Qn301A, Qn302A in order to reliably compare the input signals in1, in2. A current mirror was therefore comprised of the NMOS transistors Qn303A, Qn304A connected to a diode-connected NMOS transistor Qn305A through a common gate.
Also in the circuit of the related art 3, the PMOS transistors QP303A, Qp304A, Qp305A were connected between the power supply VDD and the drains of the NMOS transistors Qn303A, Qn304A, Qn305A. These PMOS transistors QP303A, Qp304A, Qp305A comprise a current mirror circuit by means of a common gate connection with the diode-connected PMOS transistor Qp306A. The source of the NMOS transistor Qn305A was directly connected to ground and the PMOS transistor Qp306A was connected to ground by way of the power supply I.
Therefore, the level shift circuit of the related art 3 satisfied the conditions necessary to permit achieving a stable level shift operation, by supplying the input signals in1, in2 to the gates of the NMOS transistors Qn301A, Qn302A after applying a DC shift, so that the amplitude of the input signals in1, in2 was a voltage sufficient to turn on the NMOS transistors Qn301A, Qn302A, even in a level shift circuit of TFT (thin film transistors) with a large threshold voltage Vt. However, lowering the supply voltage VDD to maintain a dynamic range for the circuit was difficult, and consequently the problem occurred that a TFT circuit system with low power consumption could not be achieved.
A sampling latch cell circuit of the related art having a level shift function comprised of CMOS devices is shown in FIG. 10B. This latch cell circuit of the related art is comprised basically of a comparator structure CMOS latch cell 101 having an N channel (hereafter simply NMOS) MOS transistor Qn101B with the input signal in1 as the gate input and a source connected to ground, an NMOS transistor Qn102B with the input signal in2 as the gate input and a source connected to ground, a P channel MOS transistor (hereafter simply PMOS) Qp101B connected between the power supply VDD and the drain of NMOS transistor Qn101B and having a gate connected to the drain of the NMOS transistor Qn102B, and having a PMOS transistor Qp102B connected between the power supply VDD and the drain of NMOS transistor Qn102B and having a gate connected to the drain of the NMOS transistor Qn101B.
The drain outputs from the NMOS transistor Qn102B and Qn101B in this CMOS latch cell 101B are latched in a latch circuit 106B by way of the inverters 102B, 103B and sampling switches 104B, 105B. The other latch output of the latch circuit 106B is inverted by the inverter 107B and supplied as an output signal out, and the other latch output is inverted by the inverter 108B and supplied as xout, which is a signal inversion of the output signal out.
In the structure of the above described sampling latch circuit of the related art, a 3 volt low voltage amplitude signal is for instance input as in1, and an inverted in1 signal input as in2. These 3 volt low voltage amplitude signals in1 and in2, are temporarily boosted up to the power supply voltage VDD in the CMOS latch cell 101B, and then, after passing via the inverters 102B and 103B are sampled by the sampling pulse SP in the sampling switches 104B, 105B and stored in the latch circuit 106B. After inversion by the inverters 107B and 108B, these signals sent as the output signals out, xout.
However, the above described sampling latch circuit of the related art, the circuit is comprised of many circuit devices (or elements) so that a small surface area is cannot be achieved. Further, when comprised of circuits utilizing devices having a large threshold voltage Vth such at TFT (thin film transistors), then the voltage amplitude of the input signals in1 and in2 is too small versus the threshold voltage Vth and consequently the transistors cannot be turned on reliably, rendering the problem that the sampling operation will not function.
In contrast, the related art shown in FIG. 11B operates easily, even if the device has a high threshold voltage Vth. The sampling latch circuits of the other related art have a structure that shifts the DC level of the signal by means of a capacitor. In other words, the outputs of the switch 201B that inputs the signal in1, and the switch 202B to input the signal in2 are connected in common, and one end of the switch capacitor 203B is connected to that common point. The other end of this capacitor 203B is connected to one end respectively of the switches 204B and 205B as well as the input of the inverter 205B.
The output end of the inverter 207B is connected to the other end of the switch 205B. The other end of the switch 204B, the output of the inverter 206B and the input of the inverter 207B are connected in common, and the input of the inverter 208B is connected to that common point, and an output signal out is sent from the output of the inverter 208B.
In the structure of the above described sampling latch circuit of the related art, a switch-capacitor 203B is utilized as the comparator and the circuit operation is as follows. First of all, circuit reset is performed by setting the switches 202B, 204B on in response to an equalizing pulse Eq. Afterwards however, a low voltage amplitude input signal in1 is sampled by turning on a switch 201B in response to an equalizing pulse SP. Next, this sampled signal in1 is level shifted while being compared with the input signal in2 in the capacitor 203B, and finally latched in latch circuits 206B, 207B by a switch 205B turning on in response to a latch pulse LT.
In this way, the above sampling circuit of the related art, even with a circuit comprised of TFTs having a high threshold voltage can be easily operated by shifting the DC level of the input signal in1 by means of a capacitor 203B, and stable sampling and latch operation can be achieved. However this circuit has the problem that low current consumption is difficult to achieve since direct current must flow in the circuit during reset. Further, many types of pulses are required for circuit operation and a complex control circuit is also needed because of difficult timing control and therefore a small circuit surface area cannot be achieved.
A latch circuit of the related art 1, having a CMOS structure with a level shift function is shown in FIG. 10C. This latch circuit of the related art 1 has a structure comprised of a first and second switch 101C, 102C for inputting the first and second input signals in1, in2 in response to the latch pulse, a CMOS latch cell 103C for latching each of the signals input by means of these switches 101C, 102C, and a level shift circuit 104C to shift the level of the latch data of the CMOS latch cells 103C.
Here, the CMOS latch cell 103C is comprised of two CMOS inverters 107C and 108C connected in parallel between the power line 105C of the positive power supply VDD and the power supply line 106C of the negative power supply voltage (for instance, ground level) VSS1. The input terminal of the CMOS inverter 107C is connected to the output terminal of the other CMOS inverter 108C, and the input terminal of the CMOS inverter 108C is connected to the output terminal of the other CMOS inverter 107C.
The level shift circuit 104C is connected between the power line 105C and the power line 109C (negative power supply voltage) for voltage VSS2 having a lower voltage than the negative power supply voltage VSS1. The data latched at a low level in the CMOS latch cell 103C is level shifted from power supply voltage VSS1 to power supply voltage VSS2.
In this latch circuit of the related art 1, a low voltage amplitude signal between VDD and VSS was input as in1, and an inversion of the in1 signal was input as in2. These low voltage amplitude signals in1 and in2 are latched in the CMOS cell circuit 103C by the switches 101C and 102C turning on in response to a latch pulse, and then level shifted to a signal with an amplitude between VDD and VSS (VSS<VSS1) by means of the level shift circuit 104, and finally output as the output signals out1 and out2.
The latch circuit of the related art 2 having a level shift function is shown in FIG. 11C. This latch circuit of the related art 2 is comprised of a first and a second switch 201C and 202C to input the first and second input signals in1, in2 in response to a latch pulse, and a CMOS latch cell 203C to latch each of the signals input by way of the switches 201C and 202C.
Here, the CMOS latch cell 203C is comprised of two CMOS inverters 206C and 207C connected in parallel with a power supply line 204C and a power supply line 205C for a power supply voltage VSS2 lower than a power supply voltage VSS1. The input terminal of the CMOS inverter 206C is connected to the output terminal of the other CMOS inverter 207C, and the input terminal of the other CMOS inverter 207C is connected to the output terminal of the other CMOS inverter 206C.
In this latch circuit of the related art 2, a low voltage amplitude signal between VDD and VSS is input as in1, and an inversion of the signal in1 is input as in2. These low voltage amplitude signals in1 and in2 are latched as an amplitude signal between VDD and VSS2 in the CMOS cell circuit 203C by the switches 101C and 102C turning on in response to a latch pulse, and these amplitude signals are then output unchanged, as the output signals out1 and out2.
However, in the latch circuit of the related art 1, the installation of a level shift circuit 104C in the latter stage of the CMOS latch cell 103C was necessary so the number of devices (elements) comprising this latch circuit became large creating the problem that a circuit with a compact size (small area) could not be achieved. In the latch circuit of the related art 2 however, though installation of a level shift circuit was not necessary and the number of devices in the circuit was small compared to the latch circuit of the related art 1, the low voltage amplitude signal had to be rewritten in order to latch as a high voltage amplitude signal so that the size of the signal buffer of the previous stage was too large, also creating the problem that a circuit with a compact size (small area) could not be achieved.
However, when fabricating a drive-circuit-integrated liquid crystal display comprising a digital interface drive circuit integrated with a pixel section of polysilicon TFT on a glass substrate (liquid crystal panel) with silicon TFT (thin film transistors) arrayed in two-dimensional matrix as the pixel switching devices, a latch circuit with a small surface area is an essential factor in narrowing the width of the peripheral area (picture frame) of the pixel forming the drive circuit.
In other words, in an drive-circuit-integrated liquid crystal display, the latch circuit must be provided for each column line/each bit. Since this latch circuit is required in quantities equivalent to the number of horizontal dots times the number of bits, the inability to make the latch circuit smaller consequently leads to the problem that the width of the picture frame of the liquid crystal panel has to be made larger.
Further, in the drive-circuit-integrated liquid crystal display, mounted with a latch circuit having the above described level shift function, the current flow in the second power supply (for example the VSS2 power supply) may sometimes have to be reduced to an extremely small amount. In the drive-circuit-integrated liquid crystal display made with TFT (thin film transistors) for example, a latch circuit with a circuit configuration for horizontal drive system may be installed, while at the same time attempting to fabricate a second power supply generator circuit with TFT (thin film transistors).
In such cases, the total current flow to the second power supply generator circuit will become large on account of the large number of latch circuits with level shift function that are required. However, fabricating a power supply generator circuit with TFT (thin film transistors) that can maintain a sufficient current capacity is extremely difficult. Consequently, integrating a second power supply generator circuit onto a glass substrate with thin film transistors is difficult to achieve and leads to the problem of an increased size (surface area) of the peripheral circuit.
The latch circuit of the related art 1 and 2 is configured to perform a level shift of low voltage amplitude signals in1 and in2 between VDD to VSS1, to a signal amplitude between VDD and VSS2 however, a level shift to a third power supply voltage VDD2 (VDD2>VDD) may also be performed.
The related art is shown in FIG. 12C and FIG. 13C. FIG. 12C is an example of the related art 3 corresponding to FIG. 10C. FIG. 13C is an example of the related art 4 corresponding to FIG. 13C. The latch circuit of the related art 3 is comprised in the latter stage of a level shift circuit 104C, of a second level shift circuit 111C connected between the power supply line 109C of the power supply voltage VSS2 and the power supply line 110 of the power supply voltage VDD2 higher than the power supply voltage VDD. The latch circuit of the related art 4 on the other hand, is a CMOS latch cell 203C and connected between the power supply line 205C of the power supply voltage VSS2 and the power supply line 208C of the power supply voltage VDD2 with a voltage higher than the power supply voltage VDD.
The latch circuit of the related art 3 and the latch circuit of the related art 4 also have problems identical to the previously described latch circuit of the related art 1 and the latch circuit of the related art 2.